STAFF-SENIOR GPU POWER DESIGN VERIFICATION ENGINEER - CORK, IRELAND

Overview

Client: Our client, a leading Multinational Semiconductor Telecom Company, requires Staff or Senior GPU Power Verification Engineer for roles based in Cork City, Ireland.

Role: You will work with Architecture and Design teams to understand low power design features and create verification plans, develop a test plan document for the design features, have them reviewed with the design team, develop verification components and testbenches for low power verification, and integrate third party VIPs/UVCs as required. Create constraint random verification environment using System Verilog and UVM.

Responsibilities

• Follow company defined verification methodologies
• Perform Power Aware Verification in a random verification environment with embedded firmware running on the design
• Regress and close the required Low Power coverage metrics to ensure high quality design
• Create portable test setup and verification components that can be reused across simulation and emulation platforms
• Perform failure debug involving hardware/software co-debug
• Work with tool vendors and push the methodology to improve the verification flows
• System level RTL simulation and design verification
• Support SoC DV for their integration verification, chip bring up and post-silicon debug

Education

• Bachelor's degree in Science, Engineering, or closely related field

Experience

• 3+ years of hands-on experience in System Verilog, OVM/UVM based constrained random verification
• 3+ years in Design validation / Post-Silicon debug
• 3+ years of hands-on experience in developing verification components/UVCs, testbench for RTL verification
• 3+ years of hands-on testbench bringup, integrating third party VIPs, digital design, verification, debugging, and waveform debugging
• 2+ years of experience in UPF based Power Aware verification
• 2+ years of experience in Functional coverage model development and/or code coverage closure
• Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells

Desirable Skills

• MS degree in Electrical Engineering or equivalent; 8 years of practical experience
• Experience with Synopsys NLP (native Low Power) tool
• Working knowledge of GLS, PAGLS and scripting languages such as Perl, Python is a plus
• Power Aware Emulation verification experience
• Hardware/Software Co-verification
• Worked on Low Power coverage metrics collection and coverage closure
• Knowledge of GPU/CPU/DDR/Bus preferred
• Scripting skills using Python
• Formal verification experience (AND/OR) Low Power Formal Verification experience

Working Model

The company offers hybrid working model of 4 days onsite and 1 day from home.

Contact

For further information please contact Mícheál at Software Placements on 00353 1 or email