Research Associate - Heterogeneous Integration: Systems Architecture and Design

Research Associate - Heterogeneous Integration: Systems Architecture and Design Job Title: Research Associate - Heterogeneous Integration: Systems Architecture and Design

Posting Start Date: 18/09/2026

Job Id: 3155

School/Department: Electrical & Electronic Engineering

Work Arrangement: Full Time (Hybrid)

Contract Type: Fixed-term

Salary per annum (£): £38,784.00 - £47,389.00

Closing Date: 01/11/2026

The University of Sheffield is a remarkable place to work. Our people are at the heart of everything we do. Their diverse backgrounds, abilities and beliefs make Sheffield a world-class university.

We offer a fantastic range of benefits including a highly competitive annual leave entitlement (with the ability to purchase more), a generous pensions scheme, flexible working opportunities, a commitment to your development and wellbeing, a wide range of retail discounts, and much more. Find out more about our benefits (opens in a new window) and join us to become part of something special.

Overview CHIMES - the Centre for Heterogeneous Integrated MicroElectronic and Semiconductor Systems - is one of the UK's national semiconductor research-translation programmes, a £16.3M Innovation and Knowledge Centre led by the University of Sheffield. We are appointing a Research and Innovation Fellow in Systems Architecture and Design to its CTO Office.

This is not a conventional postdoctoral research post. Its core is landscape analysis and roadmap intelligence - reading the international state of the art in system architecture, chiplet partitioning and front-end design, identifying the gaps the UK must close, and turning that into the knowledge infrastructure a national programme runs on. A research theme of your own is developed alongside that work, not instead of it.

This post focuses on the 'logical' layer of heterogeneous integration - partitioning a system into functional chiplets and dies, specifying cross-die interfaces, and establishing the system-level architecture that determines what is integrated, how it is interconnected, and what performance, power and security properties the assembled system must deliver. This spans system-technology co-optimisation (STCO/XTCO), front-end design automation (RTL, logic synthesis, architectural exploration, floor planning, partition-aware EDA flows), chiplet interconnect standards (UCIe, CXL, die-to-die PHY), and the open Design Commons methodology CHIMES is building as its core knowledge infrastructure.

We are advertising two paired CTO Office posts in parallel: in Systems Architecture and Design (the logical layer) and a companion post in Manufacturing Pathways, Test and Supply Chain (the physical layer). The logical-to-physical handoff - where system partitioning decisions are handed from architectural intent to physical realisation - is the primary interface between the two posts, and both post holders are expected to develop working familiarity with each other's domain. Candidates whose interests span both layers are welcome to apply for both; please indicate this in your cover letter.

You will join the Microelectronics and Integrated Semiconductor Systems Team within the Quantum and Semiconductor Systems (QSS) Group - one of the UK's largest and most successful semiconductor research environments. The Team hosts Sheffield's leadership role for CHIMES , which brings together partner universities including Cambridge, Oxford, Edinburgh, Manchester, Newcastle, Strathclyde, Queen's University Belfast and King's College London, alongside the Science and Technology Facilities Council. Industrial partners include, among others, Imec, Arm, Pragmatic, Cadence, Synopsys and Siemens EDA. The CTO Office sits at the centre of the programme's technical intelligence function; you will collaborate closely with the newly established CHIMES engineering cohort, though the CTO Office and the engineering team are distinct functions.

Why this role is distinctive.

• It is a national-programme intelligence role. You will lead landscape and roadmap work that directly shapes CHIMES research priorities, demonstrator projects, and the Design Commons - work with reach across the UK ecosystem, not confined to a single lab.
• It is a deliberate platform to launch from. The post is designed to let you build a visible, fundable independent research identity and the track record to launch it - whether toward a research fellowship (RAEng, UKRI FLF, MSCA, ERC Starting), a first permanent academic appointment, or a senior role in the national semiconductor ecosystem. The four-year term gives genuine room to figure out which of those is right for you and to become competitive for it.
• You will be a named representative of CHIMES externally - at IMAPS, IEEE ECTC, DATE, Hot Chips, TechWorks DESN and equivalent forums - and a named author on Design Commons white papers, capability maps and policy briefings produced from your work.

Areas of particular interest

• System partitioning and chiplet decomposition methodologies; cross-die interface specification frameworks.
• System-technology co-optimisation (STCO/XTCO) and mission-aware partitioning under power, thermal and security constraints.
• Front-end and system-level EDA for multi-die design - partition-aware synthesis, architectural exploration, system-level floor planning, cross-die timing, die-to-die interface IP.
• Chiplet interconnect standards (UCIe, CXL, die-to-die PHY) and interoperability frameworks (3Dblox, OIF).
• Open Design Commons infrastructure and open-source EDA / RISC-V IP ecosystems.

All four cross-cutting constraints - design-for-test (DfT), design-for-power-delivery (DfP), design-for-security (DfS) and design-for-thermal-extraction (DfTh) - span the logical-physical boundary, and both post holders are expected to develop working familiarity with them regardless of primary domain.

No candidate need span all areas. Strong credibility in logical systems architecture and front-end design is the core requirement; depth in one or more of the complementary areas above is welcomed.

We particularly welcome applicants whose work has bridged from adjacent backgrounds - computer architecture, embedded systems, FPGA-based research, accelerator or hardware-software co-design, low-power or sensor or quantum-hardware systems, or high-speed PCB / board-level integration - into circuit, system and integration work. To be clear, the focus is on the systems-and-integration direction; candidates whose current work is still on the device-physics or process side are out of scope for this post, as that capability is well covered elsewhere in the QSS Group, through CHIMES partners (notably Imec), and through national semiconductor programmes.

Main duties and responsibilities Technology landscape and roadmap

• Lead the WP1 logical systems architecture domain landscape activities - structured analysis of the needs of integrators and of those seeking to integrate maturing-TRL device, circuit or interposer propositions - covering system partitioning, chiplet decomposition, cross-die interface specification, and STCO/XTCO approaches across the UK and international HI community.
• Develop and maintain CHIMES roadmaps for the logical architecture and front-end design domain, cross-referencing international roadmap assets including IEEE HIR, EU APECS, DARPA CHIPS/NGMM, SRC JUMP 2.0, imec STCO, and interoperability standards (UCIe / 3Dblox / OIF / CXL).
• Analyse front-end EDA tool gaps for heterogeneous integration - partition aware synthesis, multi die timing closure, DfT insertion at the chiplet boundary, DfS architectural patterns, power intent specification across dies (UPF/CPF), and thermal aware floorplanning.
• Conduct structured gap analysis identifying integration specific design challenges underserved by current UK and international R&D, particularly in multi vendor chiplet EDA flows, STCO, and open Design Commons infrastructure.

Leadership and ecosystem engagement

• Represent CHIMES at national and international events and policy forums (IMAPS, IEEE ECTC, TechWorks DESN, DATE, Hot Chips and equivalent), and build relationships across the design, EDA, foundry/OSAT and standards communities (IEEE, JEDEC, IPC, SEMI, UCIe Consortium).
• Contribute technical intelligence to CHIMES business and policy development - government consultation responses, policy briefings, and the programme's strategic positioning - and communicate landscape findings to the Advisory and Technical Advisory Boards.
• Work collaboratively with domain specific PDRAs recruited by CHIMES Co Investigators, aggregating contributions across the research college into coherent programme level roadmap assets, and collaborate with the companion RIF on the logical to physical handoff methodology.
• Work closely with the CHIMES Sheffield engineering team, contributing CTO Office intelligence to Design Commons and demonstrator delivery and to the programme's skills building activities.

Knowledge asset creation

• Lead the development of Design Commons white papers, capability maps and curated landscape reports in your domain, translating complex technical and ecosystem intelligence into outputs accessible to both technical and policy audiences.
• Apply and help shape the CHIMES roadmapping methodology (technology roadmapping, systems thinking, gap analysis), ensuring outputs align with international benchmarks (IEEE HIR, EU Chips JU, DARPA NGMM, SRC JUMP 2.0).
• Contribute to co created WP3 demonstrator project briefs and to Annual Reports . click apply for full job details