CPU Server Physical Design Timing Engineer - Cambridge, UK

Company:

Qualcomm Technologies International Ltd

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

About Us

At our Cambridge site we have focussed on pioneering IoT and automotive technologies, with engineering areas of excellence including, Analogue and Digital Design, Voice and Music (Hardware, Software, OEM Support, Innovation).

Cambridge is our largest office in the UK, with more than 600 team members including engineers, business strategists and support staff.

You will join the CPU team in our Cambridge office and you will be required to be onsite 5 days per week.

Where you will be working

Cambridge, located in the East of England, 50 miles north of London, is a unique and beautiful city, renowned for its world class university and the thriving cluster of high technology businesses that have grown up around it. Cambridge is well served by road and rail links, and is within easy distance of the major London airports.

About The Role

NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.

In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows. One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will have the opportunity to collaborate with Qualcomm central timing technology & methodology team and also interact with CPU implementation team to drive PPA goals of CPU. You will have the opportunity to carve out a strong professional growth path working on industry leading technology nodes N2/N3.

Key Responsibilities

• STA setup, convergence, reviews and signoff for multi mode, multi voltage domain designs of Oryon CPU Cores.
• Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
• Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.
• Evaluate multiple timing methodologies/tools on different designs and technology nodes.
• Work on automation scripts within STA/PD tools for methodology development.
• Good technical writing and communication skills, should be willing to work in a cross collaborative environment.
• Strong experience in design automation using TCL/Perl/Python.
• Familiar with digital flow design implementation RTL to GDS: ICC, Innovus, PT/Tempus.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Preferred Qualification/Skills include

• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, latch transparency handling, 0 cycle, multi cycle path handling.
• Hands on experience with STA tools - Prime time, Tempus.
• Have experience in driving timing convergence at Chip level and Hard Macro level.
• In depth knowledge cross talk noise, signal integrity, layout parasitic extraction, feed through handling.
• Knowledge of ASIC back end design flows and methods and tools (ICC2, Innovus).
• Expert in scripting languages - TCL, Perl, Python.
• Basic knowledge of device physics.

What's on Offer

Apart from working in an open, relaxed and collaborative space, you will enjoy:

• Salary, stock and performance related bonus
• Maternity/Paternity Leave
• Employee stock purchase scheme
• Matching pension schemeeducation assistance
• Relocation and immigration support
• Life, medical, income and travel insurance
• Subsidised gym membership
• Bicycle purchase scheme

Equal Opportunity Statement

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may email or call Qualcomm's toll free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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Contact Information

If you would like more information about this role, please contact Qualcomm Careers.