CONTRACT FRONT-END DESIGN ENGINEER - CORK CITY -IRELAND

Our client a leading Multinational Semiconductor Telecom requires Contract Front-End Digital Design Engineer for 6 month daily rate position based in Cork City, Ireland.

Support Foundation IP development and release activities through RTL Verilog updates, quality assurance, and release management.

Responsibilities include implementing and validating RTL design changes, managing ClearCase-based release processes, performing QA checks for Foundation IP deliverables, and enhancing release workflows through Python scripting and automation.

The role requires close collaboration across multiple global sites and cross-functional teams, with a strong focus on daily communication, coordination, and proactive issue resolution to ensure project milestones and release deadlines are met. The successful candidate will work with design, verification, integration, and program teams to deliver high-quality IP releases, improve process efficiency, and maintain configuration management and release documentation

• Translate architectural and microarchitectural specifications into robust, synthesizable RTL.

• Develop and maintain digital designs usingSystemVerilog/Verilog.

• Design and implement modules including control logic, datapaths, state machines, interfaces, and complex digital blocks.

• PerformRTL design, simulation, linting, synthesis, and timing analysis.

• Work with verification teams to develop design specifications, test plans, and functional coverage requirements.

• Debug RTL and simulation issues and resolve functional, performance, and design-quality problems.

• Analyse synthesis results and optimise designs forpower, performance, and area (PPA).

• Collaborate with physical design teams to address timing, area, and implementation-related issues.

• Participate in design reviews and contribute to coding standards, methodologies, and best practices.

• Support design bring-up and silicon debug where required.

• Contribute to improving design flows, automation, and development methodologies.

• Bachelor's or Master's degree inElectrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.

A minimum of 2 years experience in the following:

• Experience indigital IC/ASIC/SoC design.

• Strong knowledge of digital logic design and RTL development.

• Proficiency inVerilog/SystemVerilog.

• Experience with RTL simulation and debugging using industry-standard EDA tools.

• Understanding ofsynthesis, static timing analysis, clocking, resets, and design constraints.

• Familiarity with ASIC design flows from RTL through synthesis and implementation.

• Strong problem-solving and analytical skills.

• Good communication and teamwork skills.

• Experience withUVM, SystemVerilog Assertions (SVA), or formal verification.

• Knowledge ofAMBA protocols, such as AXI, AHB, or APB.

• Experience with low-power design techniques and methodologies.

• Familiarity withCDC/RDC analysis.

• Experience with synthesis and timing tools such asSynopsys Design Compiler/PrimeTimeor equivalent.

• Experience with scripting languages such asPython, Perl, or Tcl.

• Understanding of physical design concepts and RTL-to-GDSII flows.

• Experience with high-speed interfaces, CPUs, accelerators, memory subsystems, or other complex SoC components.

Digital Design RTL integration, ASIC design 2. CDC, Lint 3. Verilog/system verilog 4. AMBA protocols 5. scripting