Senior Verification Engineer - Hybrid (SystemVerilog/UVM)

A leading quantum technology firm in Cambridge is looking for a Verification/Senior Verification Engineer. In this pivotal role, you will define verification strategies, develop scalable testbenches, and maintain verification environments. The ideal candidate has strong experience in functional verification and testbench design, with skills in SystemVerilog and programming languages like C/C++ or Python. You will thrive in a collaborative environment focused on quality and innovation, with a comprehensive benefits package, including equity, medical insurance, and 28 days of annual leave.