Senior Principal RTL Design Engineer

A market leader in the design of crucial, innovative HW & SW semiconductor design tools is searching for an RTL expert to drive innovation and system architecture for their IP library, accelerating chip design, providing targeted optimization.

Key tasks:

• Collaborate within a team to design, optimize, verify, and document a library of high-quality arithmetic components for chip designers.
• Ensure components are robust, efficient, and easy to integrate.
• Define and maintain architectural standards for software and hardware integration.
• Partner with internal and external stakeholders to capture requirements and translate them into technical specifications.
• Drive innovation in system design and optimization for timing, area, and power.

Your Ideal background:

• Proven experience in HW design with (System) Verilog.
• Solid programming skills in C++, Java, or Python; experience with scripting languages (e.g., TCL) is a plus.
• Expertise in system design.
• Familiarity with formal verification and design verification methodologies.
• Knowledge of floating-point arithmetic and numerical computation is advantageous.
• Hands-on experience with simulation tools, modelling, and performance optimization.
• Excellent analytical and creative problem-solving skills.
• Strong communication skills and ability to interface with internal and external stakeholders.
• Strong academic background (Bachelor's or Master's in computer science, Software Engineering, Mathematics, Physics, or Electrical Engineering. (PhD is a plus)

Of course, this is only a snapshot of the role. For more details please reach out to Em Feely