Senior IP Design Engineer - FPGA/SoC RTL Expert

A technology consulting company is seeking a knowledgeable Senior IP Design Engineer to create high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. This hybrid position requires expertise in 100Gb Ethernet, PCIe Gen5, and Vivado/Vitis. The role involves delivering synthesis-ready designs that meet timing and integration requirements, with a strong focus on FPGA/Adaptive SoC design flow. This contract role offers a salary of £300 - £400 per day.