Senior Design for Test (DFT) Engineer

Qualifications

• 6-8 years of directly related experience in ASIC/SoC DFT.
• Expert level knowledge of DFT architecture and planning.
• Hands on experience with the Tessent DFT Tool.
• Expert level knowledge of Scan, Test Compression, At Speed Test, Memory Built In Self Test (MBIST), Logic BIST (LBIST).
• Hands on experience with Scan Insertion, Compression Insertion, On Chip Clock Control Insertion, ATPG, DFT Verification.
• Gate level simulation with SDF, silicon test bring up support, failure analysis, debug/diagnosis, and scripting (Perl/Python/Tcl).
• Team player who can forge and maintain relationships with peer organizations.
• Strong written and verbal communication skills.

Preferred Qualifications

• Experience with Cadence and Synopsys DFT tools.
• Experience with IEEE 1149 and JTAG.
• Experience with Static Timing Analysis.
• Experience with Built In Self Test (BIST).
• Experience with synthesis and DFT insertion.
• Experience with low power scan and UPF.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce and the U.S. Department of State. Applicants for this position - except U.S. Citizens, U.S. Permanent Residents, and protected individuals - review process.

Analog Devices is an equal opportunity employer.

Travel required: 10% of the time. Shift: 1st Shift/Days.