Remote Senior SerDes ASIC/SoC Design Engineer (PCIe/PHY)

Chipright is seeking a Senior RTL Design Engineer for a contract role focusing on SerDes ASIC/SoC design. This position is fully remote within the UK and CET time zones.

The ideal candidate will have over 10 years of experience in ASIC/SoC RTL design, particularly with SystemVerilog/Verilog. Key responsibilities include implementing RTL, integrating SerDes into ASIC environments, and supporting the verification process.